The present invention relates to a switch circuit device and a switch control method using the same, more particularly, to a switch circuit device which handles a high-frequency signal and a switch control method using the same.
High-frequency switch circuit devices are used for switching operations of cell phones between the transmitting operation and the receiving operation. In cell phones, there is a need for handling a signal of a large voltage amplitude without distortion. Accordingly, as disclosed in Japanese Patent Application Publication No. 2009-27487 A, a negative voltage is used as a control voltage of a switch circuit device.
The high-frequency semiconductor switch device disclosed in this patent document includes a high-frequency switch circuit, a negative voltage generator circuit and a control circuit, which are monolithically integrated in the same semiconductor substrate. Here, the high-frequency circuit switches a connection between a plurality of terminals. The control circuit is connected to the high-frequency switch circuit and the negative voltage generator circuit and feeds a control signal to the high-frequency switch circuit. The control circuit includes a level shift circuit, a diode and a transistor. The level shift circuit has a low-side power supply terminal connected to the negative voltage generator circuit and an output node connected to the high-frequency switch circuit. The level shift circuit is configured to generate the control signal fed to the high-frequency so that the low level of the control signal has a negative voltage level. The diode has an anode connected to the output node of the level shift circuit. The transistor has a drain and a source connected to the cathode of the diode and the ground, respectively. The drain and source of the transistor are switched from the off-state to the on-state before the voltage level of the output node of the level shift circuit is switched from the high level to the low level.
FIG. 1 is a circuit diagram schematically showing an exemplary configuration of a SPDT (single pole double throw) circuit device, which is one example of the high-frequency switch device. The SPDT circuit device shown in FIG. 1 includes an antenna terminal, a first port 1, a second port 2, a first switch circuitry 10a, a second switch circuitry 10b, a first driver circuit 201, a second driver circuit 200, a decoder circuit 202 and a control signal input terminal.
The first switch circuitry 10a is disposed between the antenna terminal and the first port 1. Similarly, the second switch circuitry 10b is disposed between the antenna terminal and the second port 2. The control signal input terminal is connected to the input of the decoder 202. The first output 202a of the decoder circuit 202 is connected to the input of the first driver circuit 201. The outputs of the first driver circuit 201 are connected to control signal inputs of the first switch circuitry 10a. The second output 202b of the decoder circuit 202 is connected to the input of the second driver circuit 202. The outputs of the second driver circuit 200 are connected to control signal inputs of the second switch circuitry 10b. 
In the following, a description is given of the operation of the SPDT circuit device shown in FIG. 1.
FIG. 1 shows one example in which the first switch circuitry 10a is in the on-state and the second switch circuitry 10b is in the off-state.
A first gate-side terminal G1 of the switch circuitry 10a is fed with a positive voltage VDD, and a first back-gate-side terminal BG1 is fed with the ground voltage GND. This results in that the serially-connected N-type MOS transistors 101 to 103 are each placed into the on-state between the source and drain thereof. It should be noted that the on-resistances of the N-type MOS transistors 101 to 103 cause insertion loss. To address this problem, the positive voltage VDD fed to the first gate-side terminal G1 is adjusted to the allowed maximum voltage at which reliability assurance of the N-type MOS transistors 101 to 103 is achieved.
On the other hand, a second gate-side terminal G2 and a second back-gate-side terminal BG2 are commonly fed with a negative voltage VSS. This results in that the serially-connected MOS transistors 104 to 106 are each placed into the off-state between the source and drain thereof. It is necessary that the N-type MOS transistors 104 to 106 be kept in the off-state even when a large-amplitude signal is fed to the antenna terminal and the first port 1. To address this problem, the negative voltage VSS fed to the second gate-side terminal G2 and the second back-gate-side terminal BG2 is adjusted to the allowed minimum voltage at which reliability assurance of the N-type MOS transistors 104 to 106 is achieved.
FIG. 2 is a circuit diagram schematically showing the configurations of the first and second driver circuits 201 and 200. The first driver circuit 201 includes a first level conversion circuit 203a and a first output circuit 204a. The second driver circuit 200 includes a second level conversion circuit 203b and a second output circuit 204b. The control signal input is connected to the input of the decoder 202. The first output 202a of the decoder 202 is connected to the input of the first level conversion circuit 203a. The output of the first level conversion circuit 203a is connected to the input of the first output circuit 204a. The second output 202b of the decoder circuit 202 is connected to the input of the second level conversion circuit 203b. The output of the second level conversion circuit 203b is connected to the input of the second output circuit 204b. 
In the following, a description is given of the operations of the decoder circuit 202 and the first and second driver circuits 201 and 200 shown in FIG. 2. First, the decoder circuit 202 externally receives a control signal on the control signal input. The decoder circuit 202 generates a control signal for controlling the N-type MOS transistors 101 to 103 of the first switch circuit 10a, in response to the received control signal. The generated control signal is subjected to the voltage level conversion by the first level conversion circuit 203a and then outputted by the first output circuit 204a as voltages to be applied to the gates and back-gates of the N-type MOS transistors 101 to 103 of the first switch circuitry 10a. The second driver circuit 200 operates in the same way and outputs voltages to be applied to the gates and back-gates of the N-type MOS transistors 104 to 106 of the second switch circuitry 10b. 
FIG. 3 is a circuit diagram schematically showing an example of the configurations of the output circuits 204a and 204b. The output circuits 204a and 204b each include an input IN, an inverter circuit, an N-latch circuit, a first (or second) gate-side terminal G1 (or G2) and a first (or second) back-gate-side terminal BG1 (or BG2). The inverter circuit includes a P-type MOS transistor MP1 and an N-type MOS transistor MN1. The N-latch circuit includes N-type MOS transistors MN2 and MN3.
In the following, a description is given of the operations of the output circuits 204a and 204b. The inverter circuit outputs the negative voltage VSS from the first (or second) gate-side terminal G1 (or G2) when the voltage level at the input IN is high (for example, the positive voltage VDD) and outputs the positive voltage VDD when the voltage level at the input IN is low (for example, the negative voltage VSS). The N-latch circuit outputs lower one of two input voltages fed thereto, as understood from Japanese Patent Application Publication No. 2002-25267 A. In the configuration of FIG. 3, the N-latch circuit receives the output voltage of the inverter circuit and the ground voltage, and outputs lower one of the two voltages from the first (or second) back-gate-side terminal BG1 (or BG2).
Table 1 shows the voltages at the respective terminals of the output circuits 204a and 204b shown in FIG. 3 for the setting of the switch circuitries 10a and 10b. As shown in Table 1, when one switch circuitry (10a or 10b) is in the on-state, the gates of the N-type transistors of the switch circuitry (that is, the gate-side terminal G1 or G2) are fed with the positive voltage VDD, and the back-gates (that is, the back-gate-side terminal BG1 or BG2) are fed with the ground voltage GND. When one switch circuitry (10a or 10b) is in the off-state, on the other hand, the gates of the N-type transistors of the switch circuitry are fed with the negative voltage VSS, and the back-gates (that is, the back-gate-side terminal BG1 or BG2) are also fed with the negative voltage VSS.
TABLE 1G1BG1SW SETTINGIN(Gate)(Back Gate)ON-STATEVSSVDDGNDOFF-STATEVDDVSSVSS
In association with the above-described art, Japanese Patent Application Publication No. 2009-158671 A discloses a high-frequency switch. The disclosed high-frequency switch includes n semiconductor transistors having sources and drains connected between a plurality of terminals which interface a high frequency signal. The disclosed high-frequency switch is configured such that Voff is set to a value between Vf and (Vth−Vpin/n) where Voff is a voltage which places the semiconductor transistors into the off-state when fed to the gates thereof, Vth is the threshold voltage of the semiconductor transistors, Vf is the flat band voltage of the semiconductor transistors, and Vpin is the maximum amplitude of the high-frequency signal fed to the terminals.
Japanese Patent Application Publication No. 2009-500868 discloses an ACC (accumulated charge control) floating body MOSFET. The disclosed ACC MOSFET is adapted to control the nonlinear response of the MOSFET when the MOSFET is operated in an accumulated charge regime. The disclosed ACC MOSFET includes a MOSFET and an accumulated charge sink (ACS). The MOSFET has a floating body, wherein the floating body MOSFET selectively operates in the accumulated charge regime, and wherein accumulated charges are present in the body of the floating body MOSFET when the MOSFET operates in the accumulated charge regime. The accumulated charge sink (ACS) is operatively coupled to the body of the MOSFET, wherein the ACS removes or controls the accumulated charges in the MOSFET body.
The above-described driver circuits 201 and 200 suffer from a problem of increased power consumption caused by generation of a leakage current within the driver circuits when a large-amplitude high-frequency signal is inputted between the antenna terminal and the first port 1 or the second port 2.
FIG. 4 is an equivalent circuit diagram schematically showing the configurations and operations of the output circuit 204a and the switch circuitry 10a. The configuration of the output circuit 204a is already described with reference to FIG. 3. The N-type MOS transistor 120, which is shown as being connected to the output circuit 204a in FIG. 4, schematically represents the N-type MOS transistors 101 to 103 of the switch circuitry 10a shown in FIG. 1. The resistor 121 of FIG. 4 schematically represents the transistors 107 to 109 of FIG. 1, and the transistor 119 of FIG. 4 schematically represents the resistors 113 to 115. The N-type MOS transistor 120 is shown as having a gate connected to the gate-side terminal G1 through the resistor 121, a back-gate connected to the back-gate-side terminal BG1 through the resistor 119, and a source and drain connected to the antenna terminal and the port which is set to the on-state. There are parasitic capacitances between the source and the back gate of the N-type MOS transistor 120 and between the drain and the back-gate.
When the switch circuit 10a is placed in the on-state, the voltage outputted from the gate-side output of the output circuit 204a is VDD and the voltage outputted from the back-gate-side output is GND, as is described in the explanation of FIG. 3 and Table 1. Here, a leakage current through the N-latch circuit of the output circuit 204a is generated due to a portion of the signal transmitted between the antenna circuit and the switch circuitry 10a, which is placed into the on-state. As a result, superposition of a high-frequency signal occurs in the output circuit 204a. 
FIG. 5 is a circuit diagram showing an equivalent circuit of the output circuit 204a of FIG. 4 and the route of the leak current. The equivalent circuit diagram shown in FIG. 5 is obtained by replacing the N-type MOS transistor MN3 of the circuit shown in FIG. 3 with a resistor. It should be noted that the equivalent circuit of FIG. 5 stands under conditions in which the input voltage is VSS (a negative voltage) and the switch MOS transistors to be controlled are set to the on-state.
The voltage at the back-gate side output BG1 of the output circuit 204a instantaneously becomes positive or negative due to the superposition of the high frequency signal. When the voltage at the back-gate side output BG1 is positive, the gate-to-source Vgs of the N-type MOS transistor MN2 is negative and the N-type MOS transistor MN2 is kept in the off-state. When the voltage at the back-gate side output BG1 of the output circuit 204a is negative, however, the gate-to-source voltage Vgs of the N-type MOS transistor MN2 is positive and the N-type MOS transistor MN2 is placed into the on-state or into a state in which the N-type MOS transistor MN2 operates in the sub-threshold region. In this case, as shown in FIG. 5, a leakage current is generated which passes a route from the supply line of the positive voltage VDD to the ground via the P-type MOS transistor MP1 of the inverter circuit, the N-type MOS transistors MN2 and MN3 of the N-latch circuit.
FIG. 6 is a waveform diagram showing the waveform of the leakage current caused by the superposition of the high-frequency signal via the output circuit shown in FIG. 3. In the waveform diagram of FIG. 6, the broken line indicates the time-dependent changes in the high-frequency signal and the solid line indicates the time-dependent changes in the leakage current. As is understood from FIG. 6, the output circuit shown in FIG. 3 performs half-wave rectification in which a current flows from the supply line of the positive power supply voltage VDD to the ground for half of each period of the high-frequency signal.
FIG. 7 is a waveform diagram showing the gate-to-source voltage Vgs of the N-type MOS transistor MN2 for a case when a large-amplitude signal is fed to the antenna terminal in the output circuit shown in FIG. 3. FIG. 8 is a waveform diagram showing the current flowing through the N-type MOS transistor MN2 for a case when a large-amplitude signal is fed to the antenna terminal in the output circuit 204a shown in FIG. 3. As is understood from FIGS. 7 and 8, a large current flows for half of each period.
FIG. 9 is a graph showing a comparison of results of numerical simulations of the relation between the input signal power into the antenna terminal and the current consumption. In FIG. 9, the vertical axis represents the input signal power into the antenna terminal and the horizontal axis represents the current consumption of the circuit. The solid line indicates the current consumption of the output circuit shown in FIG. 3, and the broken line indicates that of one embodiment of the present invention, which is described later. As is understood from FIG. 9, the output circuit of FIG. 3 exhibits an increase in the current consumption as the increase in the signal power inputted to the antenna terminal.